Placement grid, manufacturing grid explanation

The manufacturing grid is the smallest resolution of your technology process. The value can be found in the tech lef file, for example:

MANUFACTURINGGRID 0.005 ;

 but I always double-check with the sign-off DRC deck to make sure this is correct. Any shapes created in your design must align to this grid, otherwise you will get DRC errors

Cells actually are aligned with the "placement" grid, which is a multiple of the manufacturing grid. The placement grid is really made up of the rows in your floorplan. The rows are composed of SITEs. For example, in the LEF you will see that each std cell references a SITE that is defined either in the std cell LEF or the tech LEF. The std cell SITE will have the same height as your std cells, but the width will be as small as your smallest filler cell. When you create ROWs in your floorplan, you are really laying out a bunch of these SITEs side by side. The std cells then get placed on these rows.
So, as long as you have everything defined correctly - manufacturing grid, SITE definitions, and ROWs in your floorplan, you should always be aligned with the manufacturing grid. Encounter knows what the grid is, and will only place things (cells and wires) on grid. Occasionally, you will find something offgrid - maybe a hand-placed cell, or a hand-routed wire, where you either turned off DRC checks or maybe entered bad coordinates directly into a fp or DEF file. But these days, you really have to work pretty hard to get something offgrid. :-)

site in lef file

A site is a defination (a rectangle, I think) for placing a object. For example, all the standard celll use the same site.

Physical design clean netlist

The netlist that is input to physcial design should not have any
assign statements, unmapped logic( logic not mapped to any tech cells), combinational timing loops, 1'b0 and 1'b1 statements.

All the ports of cell instances even though they are not connected should be present or defined in the netlist.

In order that the unconnected pins are not removed from the netlist for a cell instantiation use the below command in dc shell

set verilogout_show_unconnected_pins true

The assign statements are generated in the netlist due to the following reasons.
1) feedthroughs ( input directly assinged to output; to avoid this use the buffer in betwn them)
2) multi ports nets ( two outputs directly driving the same net)
3) tri-state drivers in the design at the intermediate level ( tri-state drivers are used only at the IO level of design in ASIC0

To avoid the assign statements in the netlist use the following command

set_fix_multiple_port_nets  -feedthroughs -outputs -buffer_constants -all

Formula to calculate the distance between adjacent macros

                                                     No of pins x metal pitch
Distance between the macros = -------------------------------
                                                    (no of metal layers used /2)

Consider one horizontal and vertical metal layer as one resource.

For 4 ML process, the denominator comes out to 2 and for 6 ML process it comes out to 3.

Finally calculate the value for  two adjacent macros by doubling the above value

Halo,blockage,fence, region definitions

Halo: Is not a hard constraint.


Suppose say, a routing halo, It won't stop you routing on the specified place if you give halo there.

But, It would certainly stop you from routing in the specified blockage.

Fence: If you have different modules defined in your netlist you would generally prefer them to keep in a specified area where you don't want to keep other module cells.

Tool neither allow other group cells to sit in that perticular fence nor allow the cells from the group out of fence.

Guide: You have the flexibility of moving the cells in and out of the design area.

Region: You could move other group cells into the region but not the region cells to out of the area.

All these are the ways of representations to tell the tool what to do exactly.

difference between placement blockage and Halo?

placement blockage and halo used to block other cell like standard cell or other macro to be placed in that area. So both placement blockage and halo have the same functionality.


THe different between them is halo stick with the macro like EBB. If EBB move, the halo move with it. But placement blockage will stick to the same location which you have defined for them. So for summary, halo move with the EBB movement but placement blockage location will remain although your macro move.

Useful AWK scripting commands

AWK SCRIPTING



Adding sth to a file


$NF is the value of the last field in the line in awk , $NF-1 is the last but one field


$0 is the entire line



grep PIN FB_041509_newpins.lef
awk '{print $2 "()"}'   this command greps all lines with PIN and
selects $2 only and writes to new file and adds () after $2 in every line


awk '{print $2 "()"}




awk '/PIN/ {print $1 $2}' filename ==> prints the output with $1 and $2 values side by side w/o any space




awk '/PIN/ {print $1,$2}' filename ==> prints the output with $1 and $2 values side by side with space
OR


awk '/PIN/ {print $1 " " $2}' filename ==> prints the output with $1 and $2 values side by side with space




awk '/foo/ { print $0 }' /etc/passwd this is command searches for foo in file passwd and prints the entire line having foo



awk '/start/, /stop/' file # Print all lines between start/stop pairs (not working)




awk '{print ; print ""}' FB_041509_newpins.lef to include line spaces between lines in a file




{ printf("The sum on line %d is %.0f.\n", NR, $1+$2) } in awk




awk '{ printf("the port of FB of %d is %f \n", NR, $2) }' FB_041509_newpins.lef



NR is the number of lines print NF prints all the line nos one by one in file


NF is the no of fields in a line and (print NF) prints all the fields of each line one by one




awk '/PIN/ {print $1; print $2}' FB_041509_newpins.lef prints $1 in one line and $2 in next line






awk '$1~/^C/' test.sp line beginning with C




PIN vcc after grep or search for PIN (the same line having PIN)


PIN vdd


OUTPUT is like this


PIN


vcc


PIN


vdd






awk '{print "-" " "$1 " " "il_biobuf_assp" " " "+" " " "PLACED" " " "(" " " $2 " "$3 " " ")" " " "S" }' newpadfile > compfile






awk '{print ; print " " ";"}' compfile > compfile_total ==> this command inserts ; in the every nextline of file compfile



egrep "Layout Primary Cell:

TOTAL DRC Results Generated:" oan211d2.report
awk '{ cell = $NF;getline;print cell,$(NF-1),$NF;}'


==============AWK GETLINE=================


AWK getline is important and used when we want to print the output by operating on more than one line




awk '{cell = $NF; getline;name = $4; getline;print cell,name,$3}' testfile ==> this command reads NF, $4 and $3 words from three different lines of the file testfile


IN the above command getline will get the next line in the file


awk '{ cell = $NF;getline;print cell,$(NF-1),$NF;}'




=====================================VI COMMANDS===========================================

useful Vi editor commands - text replacement and etc VISUAL BLOCK editing

==============VI COMMANDS===========================================


:80,90s/text/replacetext/g -- command to replace a text within certain lines


:70,99w >> filename (to append text from a file betn line nos to filename )


:n1,n2w file Write lines n1 to n2 to file


:n1,n2w >> file Append lines n1 to n2 to file


:1,10w file write lines 1 through 10 to file newfile


:340,$w >> file write lines 340 through the end of the file and append to file newfile





:33,224s/^/hh/ - insert the string 'hh' at the beginning of lines


:33,224s/$/hh/ - insert the string 'hh' at the ending of lines




:g/read/p - prints all occurances of `read' [kind of like a Unix grep]



% Display current filename





CTRL G shows the total no of lines in a file



:%s/text/replacetext/g to replace text


:uparrow for the above replacement command



:3,18d delete lines 3 through 18


ln -s file_name link_name





gf to move to a file in vi editor to come back type :bd or :e#


cat encounter.log
grep error
more


(VISUAL BLOCK) CTRL-V select lines to place text and type SHIFT I and type text u want and press escape

All about awk

Awk script format    awk ’/regular expression/ { print }’ filename
/pattern1/ { actions… }
/pattern2/ { actions… }
BEGIN { actions… } these actions happen before input is read!
END { actions… }    these actions happen after all the input is read!                                                             

Awk creates the variables $1, $2, $3… that correspond to the resulting fields (just like a shell script).
$0 is the entire line.
Awk automatically splits each line of input on the field separator FS (by default whitespace).

NF number of fields in the current record or the last word in the line
NR number of the current record (line)

All about sed - stream editor

Sed is used to do substitution (append, replace, insert, delete, substitute,
translate, print, copy, paste,…etc)   in files and create a new file w/o changing the first file.

sed 's/pat1/pat2/g' infile outfile  --> substitutes pat1 with pat2 in infile and creates a new file outfile.

By default sed prints each line at the std out.

Sed at command line will have below options

sed  [-n] –f script file file(s)
-or-

sed  [-n] [–e] ‘command’  files(s)

sed -f   script     => -f  indicates a sed script is given in command line

sed -n                => doesn't print the output in std out

sed -e                => when multiple sed commands are given this option is used

Some Commands
d delete line  
p print line   
h copy to temp buffer
g paste (replace with temp buffer)

EXAMPLES

Lines containing a pattern can be deleted by
sed -n ’/rexp/d’

sed -n  '/rexp/!d'  this command deletes thelines not containing the pattern

sed -n '/[0-9]/p' prints lines that contain any digits.

 sed ‘1,5/d’ somefile

prints everything but the first 5 lines of the file somefile
(same as tail +6 somefile).

> sed –n ‘/foo/p’ /usr/dict/words

just like grep foo /usr/dict/words

> sed –n ‘/START/,/STOP/p’
prints everything from STDIN between
a line that contains START and one the contains STOP

substitution examples
sed ‘s/[wW]indows/Unix/g’   substitues windows or Windows with Unix

For example, to substitute "1" with "2" only in the fifth and sixth lines of the sample file's output, the command would be:

$ sed '5,6 s/1/2/' myfile.txt

Suppose that it would be desirable for "1" to be substituted with "2," but only after the word "two" and not throughout every line. This can be accomplished by specifying that a match is to be found before giving the substitute command:

$ sed '/two/ s/1/2/' myfile.txt

The up carat (^) signifies the beginning of a line, thus

sed '/^two/ d' myfile.txt

would only delete the line if "two" were the first three characters of the line.

·  The dollar sign ($) represents the end of the file, or the end of a line, thus

sed '/two$/ d' myfile.txt

would delete the line only if "two" were the last three characters of the line.

The result of putting these two together:

sed '/^$/ d' {filename}

deletes all blank lines from a file. For example, the following substitutes "1" for "2" as well as "1" for "3" and removes any trailing lines in the file:

$ sed '/two/ s/1/2/; /three/ s/1/3/; /^$/ d' myfile.txt

one     1

two     1

three   1

one     1

two     2

two     2

three   1

$

A common use for this is to delete a header. The following command will delete all lines in a file, from the first line through to the first blank line:

sed '1,/^$/ d' {filename}

TRY these in off

• Line numbering
– Line numbers can be used to select a range of lines over which the commands will operate
– Examples
$ sed -n ’20,30p’
$ sed ’1,10d’
$ sed ’1,/ˆ$/d’
$ sed -n ’/ˆ$/,/ˆend/p’
– sed does not support relative line numbers (difference with respect to ed)

Command to remove the mail header from a saved mail message

sed  ’1,/ˆ$/d’ in_file > out_file

I/O Pads and Bond pads in ASIC

First advantages of using pads in designs are:
1) Pads enable designs to operate at different voltages (internally and externally)
2) THey have higher drive strengths to drive bigger external loads operating at higher voltages.


I/O pads have pre-driver and post-driver.
Pre-driver operating at core voltage and post-driver operating at IO voltage.
These driver internally have Level shifter to convert from IO to core voltage and vice versa, guard rings to prevent latch ups and ESD protection ckt.

Power pads for design are divided as
IO VDD power pad, IO GND pwr pad
Core VDD pwr pad, Core GND pwr pad

Pwr pads as Identified in code as having instantiations like
PVDD1DG i_lpa001( VDD); Pwr pad
PVSS1DG i_lpa002( VSS);
PDIDGZ i_lpa003( pad_a[3], a[3]); Input signal pad
PDIDGZ i_lpa004( pad_a[2], a[2]);
PDIDGZ i_lpa005( pad_a[1], a[1]);
PDIDGZ i_lpa006( pad_a[0], a[0]);
PDIDGZ i_lpa007( pad_b[3], b[3]);
PDIDGZ i_lpa008( pad_b[2], b[2]);
PDIDGZ i_lpa009( pad_b[1], b[1]);
PDIDGZ i_lpa010( pad_b[0], b[0]);
PDIDGZ i_lpa011( pad_cin, c_in);
PDO02CDG i_lpa012( c_out, pad_cout); Output signal pad
PDO02CDG i_lpa013( sum[3], pad_sum[3]);
PDO02CDG i_lpa014( sum[2], pad_sum[2]);
PDO02CDG i_lpa015( sum[1], pad_sum[1]);
PDO02CDG i_lpa016( sum[0], pad_sum[0]);

Bond pads are used to provide the connectivity from IO pads to packaging.
These are placed in between the IO pads.
Different bonding pad styles are
1) NON-CUP wire bonding (Linear or in-line and staggered types)
2) CUP wire bonding
3) Flip Chip Bonding

Linear type is used for Core limited designs and Staggered type(here more pads accomodated) for IO Limited designs.

awk for spice files editing

Text processing with awk awk is an utility to process text files. Text files are in IC design: SPICE netlists, LEF files, DEF files, Verilog, SPEF, and so on. Overview This tutorial will use the following file to demonstrate awk. It is a small SPICE netlist and an example of a file encountered by many IC designers: Tutorial file: test.sp A quick example Say you want to see from which machine you are coming from. First you do this: skew% who jgrad pts/1 Oct 20 19:34 (adsl-68-72-165-127.dsl.chcgil.ameritech.net) jgrad pts/7 Oct 20 19:44 (skew:3.0) jgrad pts/6 Oct 10 13:44 (skew:3.0) jgrad pts/8 Oct 20 20:01 (skew) We get more information than we asked for. We get a detailed report for each user on the system. Really all we wanted was the 6th word of the line that contains "adsl", which is our hostname. So we use awk and tell it to give us only those lines where the 6th word contains "adsl". And of all lines that match, print only the 6th word: skew% who | awk '$6~/adsl/ {print $6}' (adsl-68-72-165-127.dsl.chcgil.ameritech.net) We see that awk processes text line by line. It breaks each line down into words and gives them to use in variables $1, $2 etc. Then we tell awk what it should do, in this case its a simple "print" command. For this example we also used the "|" symbol, which is called a "pipe" in Unix. It tells Unix to not print the output of "who" on the screen but to "pipe" it into "awk" for further processing. We could even pipe the output of "awk" into another program: skew% who | awk '$6~/adsl/ {print $6}' | tr '-' '.' (adsl.68.72.165.127.dsl.chcgil.ameritech.net) Now the output of "awk" goes into "tr", which means "Text Replace". We use it to replace every "-" with ".". We use it to make the string look more like an IP address. We can use the parameter "-F" in awk to give it a character at with to split the line. By default that is a white space, but now we use ".". That means $1 will be "adsl", $2 will be "68" and so on: skew% who | awk '$6~/adsl/ {print $6}' | tr '-' '.' | awk -F. '{print $2 "." $3 "." $4 "." $5;}' 68.72.165.127 This is a convenient way to extract the 4 components of the IP address. We could put this line into our ".cshrc" startup script and always see our IP when we login. Save me some typing! When working with busses it happens quite frequently that we need to write out all the bus bits one by one. For example in a Pathmill config file. Or in any Spice level tool, since Spice doesn't support busses. Now imagine you have a 16 bit bus. That means a lot of typing (imagine 64 bits!). Thankfully, awk can do it for us: skew% awk 'BEGIN{for(i=0;i<16;i++)> a_0 a_1 a_2 a_3 a_4 a_5 a_6 a_7 a_8 a_9 a_10 a_11 a_12 a_13 a_14 a_15 We use awk just like C. In a for-loop we count from 0 to 15 and each iteration we print a bus bit. When we are done we use "print;" to get a new line and "exit" to exit from awk. Now all we have to do is copy and past the text into where ever we need it. And within seconds we can repeat this for bus "b" and "c". And it takes the same amount of time to print a 64-bit bus, just change the for-loop from "16" to "64". This command will save you hours of typing. In this example we use "BEGIN" to give awk a command to execute right away. Otherwise it would sit there and wait for text input. On Solaris we need the final "exit". On Linux it is not needed. Print all capacitors in the netlist! skew% awk '$1~/^C/' test.sp C142 VDD! 0 11.32551E-15 M=1.0 C143 0 17 2.29684E-15 M=1.0 This command will output only those lines in "test.sp" that start with a "C". This will give us all capacitors, since in SPICE we define a capacitor by using "C" as the first character. Note that "$1" contains the first word of the line. And "/^C/" is a regular expression that means "starts with C". Putting them together means "match all those lines where the first character starts with "C". Print all the MOS transistors! We could try the same as above: skew% awk '$1~/^M/' test.sp M172 VDD! 84 92 VDD! TSMC20P L=200E-9 W=2E-6 AD=999E-15 M173 VDD! 2 COUT net3 TSMC20P L=200E-9 W=2E-6 AD=999E-15 M399 0 16 96 0 TSMC20N L=200E-9 W=2E-6 AD=999E-15 M400 96 3 8 net4 TSMC20N L=200 W=2E-6 AD=299E-15 But note that each transistor in the Spice file contains 2 lines. With our command only the first line of each transistor is printed, because only the first line starts with an "M". We need to change our command to this: When you see an "M", start printing. And continue printing when the line starts with a "+". That is because in SPICE a "+" continues a statement from a previous line. skew% awk '$1!~/\+/ {state=0} $1~/M/ {state=1} {if(state==1) print $0}' test.sp M172 VDD! 84 92 VDD! TSMC20P L=200E-9 W=2E-6 AD=999E-15 +AS=599E-15 PD=3E-6 PS=600E-9 M=1 M173 VDD! 2 COUT net3 TSMC20P L=200E-9 W=2E-6 AD=999E-15 +AS=599E-15 PD=3E-6 PS=600E-9 M=1 M399 0 16 96 0 TSMC20N L=200E-9 W=2E-6 AD=999E-15 +AS=299E-15 PD=3E-6 PS=300E-9 M=1 M400 96 3 8 net4 TSMC20N L=200 W=2E-6 AD=299E-15 +AS=999E-15 PD=300E-9 PS=3E-6 M=1 We use the variable "state" to remember our state between lines. We also use the expression "$1!~/\+/". First, "!~" means "does not match". And "/\+/" is really "/+/", but because "+" has a special meaning we need to "escape it" by putting "\" in front of it. So we match 2 strings: Those not starting with "+" and those starting with "M". When we hit a line starting with "M" we set "state=1". This means "now we enter a part of the file we want to print". When we hit a line that does not start with "+" then we have completed whatever statement we were in, so we set "state=0". The actual printing of the line is done with "{if (state==1) print $0}". Note how similar awk is to C. We check our variable and if it is "1" then we print the line, which awk gives us as variable $0. I admit it looks akward in the beginning but this type of command comes in extremely handy. This type of programmable filtering often cannot be done any other way than with awk (and its big brother perl).

Conformal tutorial to run it

Conformal Logic Equivalence Checking (LEC)

This tutorial provides a quick getting-strated guide to Cadence Conformal logic equivalence checking. The basic flow is to input both an RTL netlist and a synthesized netlist and then have Conformal check whether both netlists are equal. Think of it as an LVS for Verilog. This is a powerful tool to get a formal proof that the output from Synthesis matches the original RTL code without having to run simulation.


The following files are used in this tutorial:

* nrd.v: The RTL netlist
* nrd.mapped.v: The gate level netlist
* cells.v: Primitive cells
* lec.do: Conformal script

(Note: The file "cells.v" is identical to the verilog simulation files in the OSU cell library, except for the DFFSR cells, which required a small modification to work with Conformal)
Starting Conformal

To start the tool, type

lec

at the command prompt. The main window will look as follows:
Reading the RTL netlist

First we read in the original RTL netlist. This will be considered as the "golden" design. It will serve as the reference for the comparison. Click on "File -> Read Design". Double-click on "nrd.v". Also note that "Type" is set to "Golden", which is correct. Load the file by clicking "OK". The dialog should look like this:
Reading the Gate-level Netlist

Next we read in the synthesized gate-level netlist. This will be called the "Revised" design. We created this by using some tool and now we want to check if it is still equal to the "golden" design.

Since this design contains standard cells we also need to read in a file with the cell definitions. Click on "File -> Read Library" and double-click on "cells.v". Then change the type from "Both" to "Revised" since the cells are only used in the Revised design. This should look as follows:

Now that the cells are loaded we can bring in the netlist. Do "File -> Read Design" and double-click on "nrd.mapped.v". Note that Conformal changed the "Type" for us to "Revised". The window should look like this:
Running the Comparison

Conformal has 2 operating modes: "Setup" and "LEC". So far we worked in "Setup" mode, where we input designs and setup pin mappings if we needed to. Now we switch to "LEC" mode. Click on the "LEC" icon the upper right hand corner. The window should look like this:

Note the table that was printed. It lists the primary inputs (PI) and primary outputs (PO) in both the revised and golden design. They are equal, which is a good sign. There could be a difference, e.g. if the revised design had differential outputs. Conformal has commands to specify those conditions.

The final step is to do "Run -> Compare" and to hit "OK". Now Conformal will reduce both designs to a canonical representation and check if they are equal. Or more precise, if all outputs compute the same Boolean expressions. In our example Conformal shows that all 18 outputs are equivalent. So we know that both netlists are equal.
Schematic view

A handy feature in Conformal is to view a schematic both netlists. This can be helpful in debugging. In the "Revised" column, click with the right mouse button on "nrd" and select "Schematic". It should look as follows:

Similarly, we can get a schematic of the golden design:
Conclusion

This short tutorial showed how to start Conformal, how to read in a golden and a revised design and how to prove that they are identical.

All steps can also be coded in a script and run on the command line:

lec -nogui -do lec.do


http://www10.edacafe.com/goto.php?encode_url=aHR0cDovL3d3dy5jaGlwdGFsay5vcmcvbW9kdWxlcy93ZnNlY3Rpb24vYXJ0aWNsZS5waHA/YXJ0aWNsZWlkPTM= view this link for more details

what is Multi mode multi corner analysis MMMC analysis

What's a Mode

A mode is defined by a set of clocks, supply voltages, timing constraints, and libraries. It can also have annotation data, such as SDF or parasitics files.
Many chip have multiple modes such as functional modes, test mode, sleep mode, and etc.

What's a Corner
A corner is defined as a set of libraries characterized for process, voltage, and temperature variations.
Corners are not dependent on functional settings; they are meant to capture variations in the manufacturing process, along with expected variations in the voltage and temperature of the environment in which the chip will operate .

commands to convert synopsys .lib format into db format

TO convert synopsys .lib format into db format, as the synopsys synthesis can only read db format
use the below commands,

read_lib
write_lib -f db -o libname

-f stands for format
-o is output