The netlist that is input to physcial design should not have any
assign statements, unmapped logic( logic not mapped to any tech cells), combinational timing loops, 1'b0 and 1'b1 statements.
All the ports of cell instances even though they are not connected should be present or defined in the netlist.
In order that the unconnected pins are not removed from the netlist for a cell instantiation use the below command in dc shell
set verilogout_show_unconnected_pins true
The assign statements are generated in the netlist due to the following reasons.
1) feedthroughs ( input directly assinged to output; to avoid this use the buffer in betwn them)
2) multi ports nets ( two outputs directly driving the same net)
3) tri-state drivers in the design at the intermediate level ( tri-state drivers are used only at the IO level of design in ASIC0
To avoid the assign statements in the netlist use the following command
set_fix_multiple_port_nets -feedthroughs -outputs -buffer_constants -all
2 comments:
Hi Kanth, nice explanation...can you please write in detail, what are the different types of netlist quality checks that we need to do and why?
what will be the effect of assign statement, floating nets or un-driven nets ,multi driven nets, combinational loop,1’b0 and 1’b1,black box present in the Netlist during input into Physical design. Please elaborate individual effect or result in Physical design
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